Method for Making a Stackable Package

ABSTRACT

The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.

CROSS REFERENCE TO RELATED APPLICATION

The application is a continuation-in-part of U.S. patent applicationSer. No. 12/586,401 filed Aug. 13, 2010.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a stacked package, stackable packageand method for making a stackable package, and more particularly to astacked package and a stackable package having a redistribution layerand a through via, and a method for making the same.

2. Description of the Related Art

FIG. 1 shows a cross-sectional view of a conventional stackable package.The conventional stackable package 1 comprises an interposer 10 and achip 20. The interposer 10 comprises a body 11, a plurality of throughvias 12, a plurality of conductive traces 13, a plurality of pads 14 anda plurality of solder balls 15. The body 11 has a first surface 111 anda second surface 112. The through vias 12 penetrate through the body 11,and are exposed to the first surface 111 and the second surface 112. Theconductive traces 13 are disposed on the first surface 111 of the body11, and electrically connected to the through vias 12. The pads 14 aredisposed on the second surface 112 of the body 11, and electricallyconnected to the through vias 12. The solder balls 15 are disposed onthe pads 14. The chip 20 is disposed on the interposer 10. The chip 20comprises a plurality of chip pads 21 and a plurality of bumps 22. Thebumps 22 are disposed between the chip pads 21 and the conductive traces13, and the chip 20 is electrically connected to the interposer 10 bythe bumps 22.

The conventional stacked package 1 has the following disadvantages. Thechip 20 of the conventional stacked package 1 is electrically connectedto exterior elements by the interposer 10. However, the interposer 10increases the thickness of the product, and the manufacturing processesof the interposer 10 is too complicated, so that the manufacturing costis increased. Moreover, the gap between the bumps 22 of the chip 20 istoo small, so that an underfill (not shown) is difficult to be formedtherein to encapsulate the bumps 22.

Therefore, it is necessary to provide a method for making a stackablepackage to solve the above problems.

SUMMARY OF THE INVENTION

The present invention is directed to a method for making a stackablepackage. The method comprises the following steps: (a) providing a firstcarrier having a surface; (b) disposing at least one chip on a surfaceof the first carrier, wherein the chip comprises a first surface, asecond surface, an active circuit layer and at least one conductive via,the active circuit layer is disposed in the chip and exposed to thesecond surface, the conductive via is disposed in the chip and connectedto the active circuit layer; (c) forming a molding compound on thesurface of the first carrier, so as to encapsulate the chip, wherein themolding compound comprises a surface attached to the surface of thefirst carrier; (d) removing the first carrier, so as to expose thesecond surface of the chip and the surface of the molding compound; (e)forming a first redistribution layer (RDL) and at least one first bump,wherein the first redistribution layer (RDL) is disposed on the secondsurface of the chip and the surface of the molding compound, andelectrically connected to the conductive via by the active circuitlayer, the first bump is disposed on the first redistribution layer(RDL), and electrically connected to the active circuit layer and theconductive via by the first redistribution layer (RDL); (f) providing asecond carrier; (g) disposing a surface of the first redistributionlayer (RDL) on the second carrier; (h) removing part of the chip andpart of the molding compound, so as to expose the conductive via to thefirst surface of the chip, and form a through via; (i) forming a secondredistribution layer (RDL) on the first surface of the chip, wherein thesecond redistribution layer (RDL) is electrically connected to thethrough via; and (j) removing the second carrier.

The present invention is further directed to a method for making astackable package. The method comprises the following steps: (a)providing a first carrier having a surface; (b) disposing at least onechip on a surface of the first carrier, wherein the chip comprises afirst surface, a second surface and an active circuit layer, the activecircuit layer is disposed in the chip and exposed to the second surface;(c) forming a molding compound on the surface of the first carrier, soas to encapsulate the chip, wherein the molding compound comprises asurface attached to the surface of the first carrier; (d) removing thefirst carrier, so as to expose the second surface of the chip and thesurface of the molding compound; (e) forming a first redistributionlayer (RDL) and at least one first bump, wherein the firstredistribution layer (RDL) is disposed on the second surface of the chipand the surface of the molding compound, and electrically connected tothe active circuit layer, the first bump is disposed on the firstredistribution layer (RDL), and electrically connected to the activecircuit layer by the first redistribution layer (RDL); (f) providing asecond carrier; (g) disposing a surface of the first redistributionlayer (RDL) on the second carrier; (h) removing part of the chip andpart of the molding compound; (i) forming at least one through via inthe chip, wherein the through via is connected to the active circuitlayer and exposed to the first surface of the chip; (j) forming a secondredistribution layer (RDL) on the first surface of the chip, wherein thesecond redistribution layer (RDL) is electrically connected to thethrough via; and (k) removing the second carrier.

Therefore, the second redistribution layer enables the stackable packageto have more flexibility to be utilized. Moreover, the through via isformed in the chip, and electrically connected to the firstredistribution layer (RDL), and an extra element is unnecessary. As aresult, the manufacturing cost and the size of the product are reduced.

The present invention is further directed to a stackable package,comprising a first chip, a second chip, a molding compound, a firstredistribution layer and a second redistribution layer. The first chiphas at least one through via. The second chip has an active circuitlayer. The molding compound encapsulates the first chip and the secondchip, and has a first surface and a second surface. Two ends of thefirst chip are exposed to the first surface and the second surface ofthe molding compound respectively, and two ends of the second chip areexposed to the first surface and the second surface of the moldingcompound respectively. The first redistribution layer is disposed on thesecond surface of the molding compound for electrically connecting theactive circuit layer of the second chip and the at least one through viaof the first chip. The second redistribution layer is disposed on thefirst surface of the molding compound for electrically connecting the atleast one through via of the first chip.

The present invention is further directed to a stackable package,comprising a molding compound, a first chip, a second chip, a firstredistribution layer and a second redistribution layer. The moldingcompound has a first surface, a second surface, a first through hole anda second through hole. The first chip is disposed in the first throughhole of the molding compound, and has a first surface, a second surfaceand at least one through via, wherein first surface and the secondsurface of first chip are exposed to the first surface and the secondsurface of the molding compound respectively. The second chip isdisposed in the second through hole of the molding compound, and has afirst surface, a second surface and an active circuit layer, whereinfirst surface and the second surface of second chip are exposed to thefirst surface and the second surface of the molding compoundrespectively, and the active circuit layer is exposed to the secondsurface of the second chip. The first redistribution layer is disposedon the second surface of the molding compound, the second surface of thefirst chip and the second surface of the second chip, for electricallyconnecting the active circuit layer of the second chip and the at toleast one through via of the first chip. The second redistribution layeris disposed on the first surface of the molding compound, the firstsurface of the first chip and the first surface of the second chip, forelectrically connecting the at least one through via of the first chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional stackable package;

FIG. 2 is a flow chart of a method for making a stackable packageaccording to a first embodiment of the present invention;

FIGS. 3 to 9 are schematic views of the method for making a stackablepackage according to the first embodiment of the present invention;

FIG. 10 is a flow chart of a method for making a stackable packageaccording to a second embodiment of the present invention;

FIGS. 11 to 18 are schematic views of the method for making a stackablepackage according to the second embodiment of the present invention; and

FIGS. 19 to 20 are schematic views showing the application of astackable package according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows a flow chart of a method for making a stackable packageaccording to a first embodiment of the present invention. First, asshown in FIG. 3 and step S21, a first carrier 31 is provided. The firstcarrier 31 has a surface 311. As shown in step S22, at least one chip 32is disposed on the surface 311 of the first carrier 31. The chip 32comprises a first surface 321, a second surface 322, an active circuitlayer 323 and at least one conductive via 326. The active circuit layer323 is disposed in the chip 32, and exposed to the second surface 322.The conductive via 326 is disposed in the chip 32, and connected to theactive circuit layer 323.

In this embodiment, the chip 32 is a known-good die, and the secondsurface 322 of the chip 32 is adhered to the surface 311 of the firstcarrier 31 by an adhesive 33. Moreover, the chip 32 further comprises atleast one hole 325. The conductive via 326 comprises a first insulatinglayer (not shown) and a conductor (not shown). The first insulatinglayer is disposed on a side wall of the hole 325, and defines a firstgroove (not shown). The conductor fills up the first groove. However, inother embodiments, a second chip (not shown) can be disposed side byside with the chip 32 on the surface 311 of the first carrier 31, andthe second chip is also a known-good die. It is understood that, theform of the second chip has no limitation, and the second chip cancomprise a conductive via or not. Moreover, the conductive via 326 canfurther comprise a second insulating layer (not shown). The conductor isonly disposed on a side wall of the first groove, and defines a secondgroove (not shown), and the second insulating layer fills up the secondgroove. In the present invention, only when the chip 32 is a known-gooddie, the chip 32 can be disposed on the first carrier 31, therefore theyield rate is increased.

As shown in FIG. 4 and step S23, a molding compound 34 is formed on thesurface 311 of the first carrier 31, so as to encapsulate the chip 32.The molding compound 34 comprises a second surface 342 attached to thesurface 311 of the first carrier 31. In this embodiment, the secondsurface 342 of the molding compound 34 is level with the second surface322 of the chip 32. The molding compound 34 is used as a support of thechip 32, so as to increase the thickness and the strength of the chip32. Therefore, a first surface 341 of the molding compound 34 is used asa supporting surface of the following manufacturing process, so as tofacilitate processing the second surface 322 of the chip 32.

As shown in FIG. 5 and step S24, the first carrier 31 is removed,preferably, the adhesive 33 is removed at the same time, so as to exposethe second surface 322 of the chip 32 and the second surface 342 of themolding compound 34. Meanwhile, the molding compound 34 is used as asupport of the chip 32, therefore a first redistribution layer (RDL) 35and at least one first bump 36 are formed, and another carrier is notneeded, as shown in step S25. The first redistribution layer (RDL) 35 isdisposed on the second surface 322 of the chip 32 and the second surface342 of the molding compound 34, and electrically connected to theconductive via 326 by the active circuit layer 323. The first bump 36 isdisposed on the first redistribution layer (RDL) 35, and electricallyconnected to the active circuit layer 323 and the conductive via 326 bythe first redistribution layer (RDL) 35.

In this embodiment, the first redistribution layer (RDL) 35 comprises aprotective layer 352, a first circuit layer 353 and an under ball metallayer (UBM) 354. The first circuit layer 353 is disposed in theprotective layer 352. The protective layer 352 has a first surface 355and a second surface 356. The second surface 356 has at least one secondopening, so as to expose part of the first circuit layer 353. The underball metal layer (UBM) 354 is disposed in the second opening, andelectrically connected to the first circuit layer 353. The first bump 36is disposed on the under ball metal layer (UBM) 354. Therefore, thefirst redistribution layer (RDL) 35 is used to re-distribute theposition of the under ball metal layer (UBM) 354 and the first bump 36,to match the position of electrical contact points of other package. Asa result, the stackable package 2 (FIG. 9) made by the method accordingto the present invention is more flexible in application.

As shown in FIG. 6 and step S26, a second carrier 37 is provided. Asshown in step S27, a surface 351 of the first redistribution layer (RDL)35 is disposed on the second carrier 37 by a glue layer 38, and the gluelayer 38 encapsulates the first bump 36. In this embodiment, the gluelayer 38 is a peelable glue layer, and formed by spin coating.Therefore, the glue layer 38 protects the first bump 36, and the secondcarrier 37 is used as a support of the first redistribution layer (RDL)35. Therefore, a surface 371 of the second carrier 37 is used as asupporting surface of the following manufacturing process, so as tofacilitate processing the first surface 341 of the molding compound 34.

As shown in FIG. 7 and step S28, part of the chip 32 and part of themolding compound 34 are removed, so as to expose the conductive via 326(FIG. 6) to the first surface 321 of the chip 32, and a through via 324is formed. That is, the conductive via 326 is substantially the same asthe through via 324, and the difference between the conductive via 326and the through via 324 is that the through via 324 is exposed to thefirst surface 321 of the chip 32. In this embodiment, the first surface321 of the chip 32 and part of the first surface 341 of the moldingcompound 34 are ground first, and then trimmed by chemical-mechanicalpolishing (CMP). However, in other embodiments, part of the chip 32 andpart of the molding compound 34 can be removed only bychemical-mechanical polishing (CMP). In this embodiment, part of thethrough via 324 is exposed to the first surface 321 of the chip 32, andforms a contact point.

As shown in FIG. 8 and step S29, a second redistribution layer (RDL) 39is formed on the first surface 321 of the chip 32. The secondredistribution layer (RDL) 39 is electrically connected to the throughvia 324. In this embodiment, the second redistribution layer (RDL) 39comprises a protective layer 391, a second circuit layer 392 and anunder ball metal layer (UBM) 393. The second circuit layer 392 isdisposed in the protective layer 391. The protective layer 391 has afirst surface 394 and a second surface 395. The second surface 395 hasat least one second opening, so as to expose part of the second circuitlayer 392. The under hail metal layer (UBM) 393 is disposed in thesecond opening, and electrically connected to the second circuit layer392. Therefore, the second redistribution layer (RDL) 39 is used tore-distribute the position of the contact point of the through via 324,to match the position of electrical contact points of other package. Asa result, the stackable package 2 (FIG. 9) made by the method accordingto the present invention is more flexible in application.

As shown in FIG. 9 and step S30, the second carrier 37 and the gluelayer 38 are removed, and meanwhile, the stackable package 2 accordingto the present invention is formed. Preferably, the glue layer 38 canchoose to be softened by heated or under ultraviolet ray according tothe characteristic of the material of the glue layer 38, so as to removethe glue layer 38. In this embodiment, the glue layer 38 is a peelablematerial with better thermoplasticity, so that the glue layer 38 can besoftened by heating, so as to remove the glue layer 38. However, inother embodiments, the glue layer 38 can be a material that can besoftened under ultraviolet ray, so that the glue layer 38 can besoftened by providing ultraviolet ray, so as to remove the glue layer38. Therefore, the glue layer 38 protects the first bump 36 during themanufacturing process.

FIG. 10 shows a flow chart of a method for making a stackable packageaccording to a second embodiment of the present invention. FIGS. 11 to18 show schematic views of the method for making a stackable packageaccording to the second embodiment of the present invention. The methodfor making a stackable package according to the second embodiment issubstantially the same as the method for making a stackable packageaccording to the first embodiment (FIGS. 3 to 9), and the same elementsare designated by the same reference numbers.

The difference between the method according to the second embodiment andthe method according to the first embodiment is that after the firstcarrier 31 is provided (step S31), the chip 32, which does not comprisethe conductive via 326 as shown in FIG. 11, is disposed on the surface311 of the first carrier 31 (step S32). Then, the same processes as themethod according to the first embodiment are conducted, that is, asshown in FIG. 12, the molding compound 34 are formed (step S33). Then,as shown in FIG. 13, the first carrier 31 is removed (step S34).Meanwhile, the molding compound 34 is used as a support of the chip 32,therefore the first redistribution layer (RDL) 35 and the first bump 36are formed (step S35), and another carrier is not needed. Then, as shownin FIG. 14, the second carrier 37 is provided (step S36), and thesurface 351 of the first redistribution layer (RDL) 35 is disposed onthe second carrier 37 by the glue layer 38 (step S37). Then, as shown inFIG. 15, part of the chip 32 and part of the molding compound 34 (stepS38) are removed.

Then, as shown in FIG. 16, a through via 324 is formed in the chip 32(step S39). The through via 324 is connected to the active circuit layer323, and exposed to the first surface 321 of the chip 32. In the end,the same processes as the method according to the first embodiment areconducted, that is, as shown in FIG. 17, the second redistribution layer(RDL) 39 is formed (step S40). Then, as shown in FIG. 18, the secondcarrier 37 and the glue layer 38 are removed (step S41), so as to formthe stackable package 2 according to the present invention.

Moreover, as shown in FIG. 19, after the stackable package 2 accordingto the present invention is formed, a second package 3 is furtherstacked on the stackable package 2, so as to form a double-layeredstacked package. It is understood that, at least one conductive element(for example, a second bump 40) is disposed between and electricallyconnects the second package 3 and the second redistribution layer (RDL)39 of the stackable package 2. Preferably, a third package 4 can hefurther stacked on the second package 3, so as to form a third-layeredstacked package. Preferably, the stackable package 2 is a processor, thesecond package 3 is a radio frequency (RF) device, and the third package4 is a memory. However, in other embodiments, as shown in FIG. 20, thestackable package 2 can further comprise a second chip 41 disposed sideby side with the chip 32, and the second chip 41 is also a known-gooddie. The form of the second chip 41 has no limitation, and the secondchip 41 can comprise a conductive via or not. Thus, the molding compound34 encapsulates the chip 32 and the second chip 41, and has a firstsurface 341, a second surface 342, a first through hole and a secondthrough hole. The chip 32 is disposed in the first through hole of themolding compound 34. The first surface 321 and the second surface 322 ofthe chip 32 are exposed to the first surface 341 and the second surface342 of the molding compound 34 respectively. That is, two ends of thechip 32 are exposed to the first surface 341 and the second surface 342of the molding compound 34 respectively. The second chip 41 is disposedin the second through hole of the molding compound 34. Similarly, afirst surface and a second surface of second chip 41 are exposed to thefirst surface 341 and the second surface 342 of the molding compound 34respectively. That is, two ends of the second chip 41 are exposed to thefirst surface 341, and the second surface 342 of the molding compound 34respectively. The first redistribution layer 35 is disposed on thesecond surface 342 of the molding compound 34 for electricallyconnecting the active circuit layer of the second chip 41 and thethrough via 324 of the chip 32, and the second redistribution layer 39is disposed on the first surface 341 of the molding compound 34 forelectrically connecting the through via 324 of the chip 32. Therefore,the second redistribution layer (RDL) 39 is used to re-distribute theposition of the contact point of the through via 324, to match theposition of electrical contact points of other package. As a result, thestackable package 2 (FIG. 9) made by the method according to the presentinvention is more flexible in application, for example, the stackablepackage 2 according to the present invention can be applied to the threefollowing situation. First, the molding compound 34 of the stackablepackage 2 encapsulates a plurality of chips 32, and after anotherpackage having the same size of the stackable package 2 is stackedthereon, a singulation process is conducted. Second, the moldingcompound 34 of the stackable package 2 encapsulates a plurality of chips32, and after a plurality of chips are stacked thereon, a singulationprocess is conducted. Third, a singulation process is conducted to thestackable package 2 first, and then, another chip is stacked thereon.Moreover, the through via 324 is formed in the chip 32, and electricallyconnected to the first redistribution layer (RDL) 35, and an extraelement is unnecessary. As a result, the manufacturing cost and the sizeof the product are reduced.

While several embodiments of the present invention have been illustratedand described, various modifications and improvements can he made bythose skilled in the art. The embodiments of the present invention aretherefore described in an illustrative but not restrictive sense. It isintended that the present invention should not be limited to theparticular forms as illustrated, and that all modifications whichmaintain the spirit and scope of the present invention are within thescope defined by the appended claims.

1. A stackable package, comprising: a first chip having at least onethrough via; a second chip having an active circuit layer; a moldingcompound encapsulating the first chip and the second chip, and having afirst surface and a second surface, wherein two ends of the first chipare exposed to the first surface and the second surface of the moldingcompound respectively, and two ends of the second chip are exposed tothe first surface and the second surface of the molding compoundrespectively; a first redistribution layer disposed on the secondsurface of the molding compound for electrically connecting the activecircuit layer of the second chip and the at least one through via of thefirst chip; and a second redistribution layer disposed on the firstsurface of the molding compound for electrically connecting the at leastone through via of the first chip.
 2. The stackable package as claimedin claim 1, wherein the second chip is a known-good die.
 3. Thestackable package as claimed in claim 1, wherein the first chip furthercomprises at least one hole, the through via comprises a firstinsulating layer and a conductor, the first insulating layer is disposedon a side wall of the hole and defines a first groove, and the conductorfills up the first groove.
 4. The stackable package as claimed in claim1, wherein the first chip further comprises at least one hole, thethrough via comprises a first insulating layer, a conductor and a secondinsulating layer, the first insulating layer is disposed on a side wallof the hole and defines a first groove, the conductor is only disposedon a side wall of the first groove and defines a second groove, and thesecond insulating layer fills up the second groove.
 5. The stackablepackage as claimed in claim 1, wherein the first redistribution layercomprises a protective layer, a first circuit layer and an under ballmetal layer (UBM), the first circuit layer is disposed in the protectivelayer, the protective layer has a first surface and a second surface,the second surface has at least one second opening, so as to expose partof the first circuit layer, the under ball metal layer (UBM) is disposedin the second opening, and electrically connected to the first circuitlayer.
 6. The stackable package as claimed in claim 1, wherein thesecond redistribution layer comprises a protective layer, a secondcircuit layer and an under ball metal layer (UBM), the second circuitlayer is disposed in the protective layer, the protective layer has afirst surface and a second surface, the second surface has at least onesecond opening, so as to expose part of the second circuit layer, theunder ball metal layer (UBM) is disposed in the second opening, andelectrically connected to the second circuit layer.
 7. A stackablepackage, comprising: a molding compound having a first surface, a secondsurface, a first through hole and a second through hole; a first chipdisposed in the first through hole of the molding compound, and having afirst surface, a second surface and at least one through via, whereinfirst surface and the second surface of first chip are exposed to thefirst surface and the second surface of the molding compoundrespectively; a second chip disposed in the second through hole of themolding compound, and having a first surface, a second surface and anactive circuit layer, wherein first surface and the second surface ofsecond chip are exposed to the first surface and the second surface ofthe molding compound respectively, and the active circuit layer isexposed to the second surface of the second chip; a first redistributionlayer disposed on the second surface of the molding compound, the secondsurface of the first chip and the second surface of the second chip, forelectrically connecting the active circuit layer of the second chip andthe at least one through via of the first chip; and a secondredistribution layer disposed on the first surface of the moldingcompound, the first surface of the first chip and the first surface ofthe second chip, for electrically connecting the at least one throughvia of the first chip.
 8. The stackable package as claimed in claim 7,wherein the second chip is a known-good die.
 9. The stackable package asclaimed in claim 7, wherein the second surface of the molding compoundis level with the second surface of the first chip and the secondsurface of the second chip.
 10. The stackable package as claimed inclaim 7, wherein the first chip further comprises at least one hole, thethrough via comprises a first insulating layer and a conductor, thefirst insulating layer is disposed on a side wall of the hole anddefines a first groove, and the conductor fills up the first groove. 11.The stackable package as claimed in claim 7, wherein the first chipfurther comprises at least one hole, the through via comprises a firstinsulating layer, a conductor and a second insulating layer, the firstinsulating layer is disposed on a side wall of the hole and defines afirst groove, the conductor is only disposed on a side wall of the firstgroove and defines a second groove, and the second insulating layerfills up the second groove.
 12. The stackable package as claimed inclaim 7, wherein the first redistribution layer comprises a protectivelayer, a first circuit layer and an under ball metal layer (UBM), thefirst circuit layer is disposed in the protective layer, the protectivelayer has a first surface and a second surface, the second surface hasat least one second opening, so as to expose part of the first circuitlayer, the under ball metal layer (UBM) is disposed in the secondopening, and electrically connected to the first circuit layer.
 13. Thestackable package as claimed in claim 7, wherein the secondredistribution layer comprises a protective layer, a second circuitlayer and an under ball metal layer (UBM), the second circuit layer isdisposed in the protective layer, the protective layer has a firstsurface and a second surface, the second surface has at least one secondopening, so as to expose part of the second circuit layer, the underball metal layer (UBM) is disposed in the second opening, andelectrically connected to the second circuit layer.
 14. A stackedpackage, comprising: a stackable package, comprising: a first chiphaving at least one through via; a second chip having an active circuitlayer; a molding compound encapsulating the first chip and the secondchip, and having a first surface and a second surface, wherein two endsof the first chip are exposed to the first surface and the secondsurface of the molding compound respectively, and two ends of the secondchip are exposed to the first surface and the second surface of themolding compound respectively; a first redistribution layer disposed onthe second surface of the molding compound for electrically connectingthe active circuit layer of the second chip and the at least one throughvia of the first chip; and a second redistribution layer disposed on thefirst surface of the molding compound for electrically connecting the atleast one through via of the first chip; a second package stacked on thestackable package; and at least one conductive element disposed betweenthe stackable package and the second package, for electricallyconnecting the second package and the second redistribution layer of thestackable package;
 15. The stacked package as claimed in claim 14,wherein the second chip is a known-good die.
 16. The stacked package asclaimed in claim 14, further comprising a third package stacked on thesecond package.
 17. The stacked package as claimed in claim 14, furtherat least one first bump disposed on the first redistribution layer, andelectrically connected to the through via of the first chip and theactive circuit layer of the second chip by the first redistributionlayer.
 18. The stacked package as claimed in claim 14, wherein the firstchip further comprises at least one hole, the through via comprises afirst insulating layer and a conductor, the first insulating layer isdisposed on a side wall of the hole and defines a first groove, and theconductor fills up the first groove.
 19. The stacked package as claimedin claim 14, wherein the first chip further comprises at least one hole,the through via comprises a first insulating layer, a conductor and asecond insulating layer, the first insulating layer is disposed on aside wall of the hole and defines a first groove, the conductor is onlydisposed on a side wall of the first groove and defines a second groove,and the second insulating layer fills up the second groove.